1. Field of the Invention
This invention relates in general to semiconductor devices and more specifically to forming a pattern for structures of a semiconductor device.
2. Description of the Related Art
FinFETs (e.g. MIGFets, ITFet, multiple fin FinFETs) include vertical channel regions located in semiconductor fin structures. An advantage with some types of finFETs is that a channel width dimension of a FinFET is located along the vertical height of the fin, there by allowing for more transistor drive current per die area. Such may also be true of other types of transistors having vertical channel structures and substantially horizontal carrier transport.
With some FinFETs, the width of the fin structure is usually at the critical dimension of the lithographic process. Some techniques for further reducing fin width include forming a first fin or other type of structure and then forming spacers adjacent to the first fin. The spacers adjacent to the first fin are then used to pattern the semiconductor fin structures.
One challenge of using spacers to define the semiconductor fin structures is that the first fin may have to meet height-to-width ratio parameters for proper spacer formation. Accordingly, the distance between the resultant two spacers (and subsequently between the two semiconductor fin structures) maybe somewhat more separated than desired.
What is needed is an improved process for forming a pattern for a structure in a semiconductor device.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The Figures are not necessarily drawn to scale.